6 comments:
Patch Set #41, Line 7: Add dram control register define and bits define
Define DRAM registers and APIs
File src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h:
Patch Set #41, Line 111: DutyScan_K_DQ
Uppercase for enums
/* frequency set point:
* 0 means lower,un-terminated freq;
* 1 means higher,terminated freq
*/
Format:
/*
* frequency set point:
* 0 means lower, un-terminated freq;
* 1 means higher, terminated freq
*/
Patch Set #41, Line 276: u8 dqs_final_delay[2][2]
Either
u8 dqs_final_delay[RANK_MAX][DQS_NUMBER]
or
u8 *dqs_final_delay
Patch Set #41, Line 284: calType
lowercase
Patch Set #41, Line 285: u1VrefScanEnable
lowercase
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