[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )

Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
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Patch Set 3: -Code-Review

(1 comment)

https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@58 
PS3, Line 58: MTRR: WB selected as default type.
> Please check the mask value for MTRR: 5 its basically ignoring WC to accommodate the BIOS MTRRs […]

I see. If WRCOMB type is removed, it means we've ran out of variabke MTRRs, which is not good.

So, is there anything inside the 0x77000000 - 0x7b000000 memory range that needs to be marked as uncachable?