Attention is currently required from: Furquan Shaikh, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(5 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/24129573_107bea52 PS34, Line 60: .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_CLK_SRC_ALWAYS_ON, What's the purpose of ClkReq if using a free-running ClkSrc?
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/db0099da_11ce0ae3 PS34, Line 264: config->pch_pcie_rp[i] To save some redundancy, I would use a pointer as follows:
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { const struct pcie_rp_config *const rp_cfg = config->pch_pcie_rp[i];
params->PcieRpL1Substates[i] = get_l1_substate_control(rp_cfg->PcieRpL1Substates);
params->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); params->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); params->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); params->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); }
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/5a24ca80_97137cbb PS34, Line 25: cfg nit: pass pointers instead? It should be more efficient than passing by copy
https://review.coreboot.org/c/coreboot/+/48340/comment/f1d89fc2_f7822fd1 PS34, Line 33: + I'd use a bitwise OR here, but it's not a big deal
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/9b9ed101_e4965781 PS34, Line 17: 0x80 This is what the current FSP binaries use, but it could change in the future.