[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/cpu/car: Enable caching before FSP-T

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38252 )

Change subject: soc/intel/common/block/cpu/car: Enable caching before FSP-T
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38252/6/src/cpu/x86/16bit/entry16.i... 
File src/cpu/x86/16bit/entry16.inc:

https://review.coreboot.org/c/coreboot/+/38252/6/src/cpu/x86/16bit/entry16.i... 
PS6, Line 134: #else
> given that you just want to avoid setting 2 bits depending on the bootguard bit, how about the follo […]

Small typo, should be:
    andl	$(~0x60000000), %ebx