[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/espi_util: espi_send_command: improve error message

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44352 )

Change subject: soc/amd/common/espi_util: espi_send_command: improve error message
......................................................................

soc/amd/common/espi_util: espi_send_command: improve error message

It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set
in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the
command failed, so we expect that one to be set.

Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7
Signed-off-by: Felix Held 
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/44352/1

diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 4415615..c1145d0 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -470,7 +470,7 @@
    }

if (status & ~ESPI_STATUS_DNCMD_COMPLETE) {
-		espi_show_failure(cmd, "Error: eSPI status register bits set", status);
+		espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", status);
    	return -1;
    }