[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure L1Substates for PCH Root ports

[Wonkyu Kim (Code Review)]

Hello Raj Astekar, build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Caveh Jalali, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39412

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Configure L1Substates for PCH Root ports
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soc/intel/tigerlake: Configure L1Substates for PCH Root ports

Set value for PcieRpL1Substates according to devicetree.

BUG=none
BRANCH=none
TEST=Boot up and check FSP log for PCIe config for this values

Signed-off-by: Wonkyu Kim 
Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/39412/2