[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )

Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
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Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@10 
PS3, Line 10: that one can perform SMRAM relocation faster.
But this was already happening.

https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@15 
PS3, Line 15: range as cacheable (+ reserved) and other ranges as reserve alone.
What's the motivation? If the order of operations is maintained (us doing mpinit w/ smm relocation early) one can just omit tseg from being a reserved ram resource because we've done all that work already. i.e. keep one memory map for init and the one we expose to OS as different.