[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Add ADL-P ramstage mainboard code

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )

Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code
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Patch Set 6:

(2 comments)

https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... 
File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... 
PS5, Line 91: s0ix_enable
> Yes Angel, S0ix use case is not fully enabled but system is going to lower c-state and system is goi […]

Alright. I wanted to know because S0ix entry requirements are somewhat unclear.

https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... 
PS5, Line 105: 		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
> Oh, I see them now: […]

Done