Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33740 )
Change subject: Documentation: Update soc/intel/apollolake ......................................................................
Patch Set 1:
(9 comments)
My personal agenda is as usual: Enhance flashrom to support a reasonable installation procedure. Then establish that pro- cedure in coreboot's build system and document it ;) But, as usual, this is stalled by the lack of flashrom review resources.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... File Documentation/soc/intel/apollolake/index.md:
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 4: Intel Integrated
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 8: which is a subregion of "BIOS" AFAIK, it covers the whole BIOS region.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 11: The IFWI region can be manipulated by `ifwitool`. But I wouldn't recommend it. It doesn't check if you overflow surrounding partitions when you edit a sub-partition, for instance.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 19: * Each LBP has it's own IFWI and OBB AIUI, IFWI is the whole thing, LBPs are part of the IFWI, and OBB is part of the LBP (the OBB in LBP1 is optional, in the dual LBP case).
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 20: * The last 256 KiB of the "BIOS" region are BIOS_UNUSABLE Only if you consider memory-mapping. You can still access the full region via the SPI controller. Let's say
* The BIOS region is memory-mapped at the top of 4GiB. However, the end is overlaid by an SRAM mapping. So the last 256KiB should be marked BIOS_UNUSABLE in the FMAP.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 22: Let's add here another pitfall:
* In case of 2 LBPs, the IFWI space is divided in half but each LBP should still be erase block aligned. With the usual erase block size of 4KiB, this makes the IFWI size a multiple of 8KiB. Many IFD layouts leave the last 4KiB empty to compensate for this.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 39: while the OBB contains It's part of IFWI, see above.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 47: Each LBP has their own IFWI and OBB. It allows failsafe firmware updates. Each LBP contains a Boot Partition Descriptor Table (BPDT) and a Secondary BPDT (S-BPDT). Only the BPDT partitions (boot critical) are mirrored in both LBPs, afaik.
https://review.coreboot.org/#/c/33740/1/Documentation/soc/intel/apollolake/i... PS1, Line 50: mode if LBP2 is missing. LBP2 is also supposed to contain the effective OBB in this case. But it doesn't matter with coreboot because it follows the FMAP anyway.