[coreboot-gerrit] Change in coreboot[master]: nb/amd/agesa: select ROMSTAGE_CACHED_CBMEM

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37198 )

Change subject: nb/amd/agesa: select ROMSTAGE_CACHED_CBMEM
......................................................................

Patch Set 7:

For a better overview:

```
   3:after ram initialization                          411,357 (281,617)
   4:end of romstage                                   426,279 (14,921)
 100:start of postcar                                  426,418 (138)
```

```
   3:after ram initialization                          414,538 (284,955)
  17:starting LZ4 decompress (ignore for x86)          421,713 (7,175)
  18:finished LZ4 decompress (ignore for x86)          427,201 (5,487)
 100:start of postcar                                  428,672 (1,471)
```

(By the way, *end of romstage* is missing.)

If I remember correctly, the 22 ms overall decrease is due to the difference in *cbmem post*, which accesses the flash ROM chip, and reads with the used chip has a lot of timing variations. (I think, Kyösti even verified it with the datasheet.)