For a better overview:

3:after ram initialization 411,357 (281,617)
4:end of romstage 426,279 (14,921)
100:start of postcar 426,418 (138)
3:after ram initialization 414,538 (284,955)
17:starting LZ4 decompress (ignore for x86) 421,713 (7,175)
18:finished LZ4 decompress (ignore for x86) 427,201 (5,487)
100:start of postcar 428,672 (1,471)

(By the way, *end of romstage* is missing.)

If I remember correctly, the 22 ms overall decrease is due to the difference in *cbmem post*, which accesses the flash ROM chip, and reads with the used chip has a lot of timing variations. (I think, Kyösti even verified it with the datasheet.)

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Gerrit-Project: coreboot
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Gerrit-Change-Id: I62ffe1bd646e9ddad77be240f030601790f4da4b
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