Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
soc/intel/tigerlake: update memory cfg for Tiger Lake
Update mem cfg on Tiger Lake Platform to use UPDs based on FSP 2527
BUG=150357377 BRANCH=none TEST= build volteer and boot to kernel
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40061/1
diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 864f079..b59643b 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -40,45 +40,53 @@ static void init_spd_upds(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0, uintptr_t spd_dimm1) { - mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1); + uint8_t dimm_cfg = get_dimm_cfg(spd_dimm0, spd_dimm1);
switch (channel) { case 0: + mem_cfg->DisableDimmCh0 = dimm_cfg; mem_cfg->MemorySpdPtr00 = spd_dimm0; mem_cfg->MemorySpdPtr01 = spd_dimm1; break;
case 1: + mem_cfg->DisableDimmCh1 = dimm_cfg; mem_cfg->MemorySpdPtr02 = spd_dimm0; mem_cfg->MemorySpdPtr03 = spd_dimm1; break;
case 2: + mem_cfg->DisableDimmCh2 = dimm_cfg; mem_cfg->MemorySpdPtr04 = spd_dimm0; mem_cfg->MemorySpdPtr05 = spd_dimm1; break;
case 3: + mem_cfg->DisableDimmCh3 = dimm_cfg; mem_cfg->MemorySpdPtr06 = spd_dimm0; mem_cfg->MemorySpdPtr07 = spd_dimm1; break;
case 4: + mem_cfg->DisableDimmCh4 = dimm_cfg; mem_cfg->MemorySpdPtr08 = spd_dimm0; mem_cfg->MemorySpdPtr09 = spd_dimm1; break;
case 5: + mem_cfg->DisableDimmCh5 = dimm_cfg; mem_cfg->MemorySpdPtr10 = spd_dimm0; mem_cfg->MemorySpdPtr11 = spd_dimm1; break;
case 6: + mem_cfg->DisableDimmCh6 = dimm_cfg; mem_cfg->MemorySpdPtr12 = spd_dimm0; mem_cfg->MemorySpdPtr13 = spd_dimm1; break;
case 7: + mem_cfg->DisableDimmCh7 = dimm_cfg; mem_cfg->MemorySpdPtr14 = spd_dimm0; mem_cfg->MemorySpdPtr15 = spd_dimm1; break; @@ -231,7 +239,6 @@ /* LPDDR4x does not allow interleaved memory */ mem_cfg->DqPinsInterleaved = 0; mem_cfg->ECT = board_cfg->ect; - mem_cfg->MrcSafeConfig = 0x1;
read_md_spd(info, &spd_data, &spd_len); mem_cfg->MemorySpdDataLen = spd_len;