Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
soc/intel/tigerlake: update memory cfg for Tiger Lake
Update mem cfg on Tiger Lake Platform to use UPDs based on FSP 2527
BUG=150357377 BRANCH=none TEST= build volteer and boot to kernel
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40061/1
diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 864f079..b59643b 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -40,45 +40,53 @@ static void init_spd_upds(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0, uintptr_t spd_dimm1) { - mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1); + uint8_t dimm_cfg = get_dimm_cfg(spd_dimm0, spd_dimm1);
switch (channel) { case 0: + mem_cfg->DisableDimmCh0 = dimm_cfg; mem_cfg->MemorySpdPtr00 = spd_dimm0; mem_cfg->MemorySpdPtr01 = spd_dimm1; break;
case 1: + mem_cfg->DisableDimmCh1 = dimm_cfg; mem_cfg->MemorySpdPtr02 = spd_dimm0; mem_cfg->MemorySpdPtr03 = spd_dimm1; break;
case 2: + mem_cfg->DisableDimmCh2 = dimm_cfg; mem_cfg->MemorySpdPtr04 = spd_dimm0; mem_cfg->MemorySpdPtr05 = spd_dimm1; break;
case 3: + mem_cfg->DisableDimmCh3 = dimm_cfg; mem_cfg->MemorySpdPtr06 = spd_dimm0; mem_cfg->MemorySpdPtr07 = spd_dimm1; break;
case 4: + mem_cfg->DisableDimmCh4 = dimm_cfg; mem_cfg->MemorySpdPtr08 = spd_dimm0; mem_cfg->MemorySpdPtr09 = spd_dimm1; break;
case 5: + mem_cfg->DisableDimmCh5 = dimm_cfg; mem_cfg->MemorySpdPtr10 = spd_dimm0; mem_cfg->MemorySpdPtr11 = spd_dimm1; break;
case 6: + mem_cfg->DisableDimmCh6 = dimm_cfg; mem_cfg->MemorySpdPtr12 = spd_dimm0; mem_cfg->MemorySpdPtr13 = spd_dimm1; break;
case 7: + mem_cfg->DisableDimmCh7 = dimm_cfg; mem_cfg->MemorySpdPtr14 = spd_dimm0; mem_cfg->MemorySpdPtr15 = spd_dimm1; break; @@ -231,7 +239,6 @@ /* LPDDR4x does not allow interleaved memory */ mem_cfg->DqPinsInterleaved = 0; mem_cfg->ECT = board_cfg->ect; - mem_cfg->MrcSafeConfig = 0x1;
read_md_spd(info, &spd_data, &spd_len); mem_cfg->MemorySpdDataLen = spd_len;
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
Patch Set 1: Code-Review+1
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... File src/soc/intel/tigerlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... PS1, Line 43: mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1); With this CL being merged https://review.coreboot.org/c/coreboot/+/39797.. we were hitting array out of bound since Reserved9 is only 2 elements now.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
Patch Set 1:
(2 comments)
Can you please remove the dependency of this CL on https://review.coreboot.org/c/coreboot/+/40026. Fixing of DisableDimmChX is not dependent on that CL.
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... File src/soc/intel/tigerlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... PS1, Line 43: mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1);
With this CL being merged https://review.coreboot.org/c/coreboot/+/39797.. […]
Woops. That is right. FSP UPD header change has to go in along with change in coreboot that was relying on any of the reserved UPDs. Thanks for fixing this!
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... PS1, Line 234: mem_cfg->MrcSafeConfig = 0x1; Can you please push this as a separate change as it is required after 2527 lands.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... File src/soc/intel/tigerlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... PS1, Line 43: mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1);
Woops. That is right. […]
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... File src/soc/intel/tigerlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... PS1, Line 43: mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1);
Done
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
Patch Set 1: Code-Review+1
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40061
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
soc/intel/tigerlake: update memory cfg for Tiger Lake
Update mem cfg on Tiger Lake Platform to use DisableDimmCh# UPD
BUG=150357377 BRANCH=none TEST= build volteer and boot to kernel
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40061/2
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40061
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
soc/intel/tigerlake: update memory cfg for Tiger Lake
Update mem cfg on Tiger Lake Platform to use DisableDimmCh# UPD.
BUG=150357377 BRANCH=none TEST= build volteer and boot to kernel
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40061/3
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... File src/soc/intel/tigerlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... PS1, Line 234: mem_cfg->MrcSafeConfig = 0x1;
Can you please push this as a separate change as it is required after 2527 lands.
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
Patch Set 3: Code-Review+1
(5 comments)
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@7 PS3, Line 7: update memory cfg for Tiger Lake This is a very generic title. Maybe: "Replace Reserved9 usage with DisableDimmCh# in init_spd_upds()"
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@9 PS3, Line 9: Update mem cfg This change updates memory configuration
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@9 PS3, Line 9: . It would be good to provide reference to the CL that updated the headers to introduce DisableDimmCh# instead of the Reserved field.
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@11 PS3, Line 11: 150357377 b:
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@13 PS3, Line 13: build volteer and boot to kernel Did you try disabling DIMMs by setting different configurations?
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40061
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD ......................................................................
soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD
This change updates memory configuration on Tiger Lake Platform to replace "Reserved9" with "DisableDimmCh#" UPD in init_spd_upds(). For reference https://review.coreboot.org/c/coreboot/+/39797 added "DisableDimmCh#" UPD
BUG=b:150357377 BRANCH=none TEST= build volteer and boot to kernel
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40061/4
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40061
to look at the new patch set (#5).
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD ......................................................................
soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD
This change updates memory configuration on Tiger Lake Platform to replace "Reserved9" with "DisableDimmCh#" UPD in init_spd_upds(). For reference https://review.coreboot.org/c/coreboot/+/39797 added "DisableDimmCh#" UPD
BUG=b:150357377 BRANCH=none TEST= build volteer and boot to kernel
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40061/5
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD ......................................................................
Patch Set 5: Code-Review+2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@7 PS3, Line 7: update memory cfg for Tiger Lake
This is a very generic title. […]
Done
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@9 PS3, Line 9: .
It would be good to provide reference to the CL that updated the headers to introduce DisableDimmCh# […]
Done
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@9 PS3, Line 9: Update mem cfg
This change updates memory configuration
Done
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@11 PS3, Line 11: 150357377
b:
Done
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@13 PS3, Line 13: build volteer and boot to kernel
Did you try disabling DIMMs by setting different configurations?
No, I did not try those experiments. Checked the default config
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@13 PS3, Line 13: build volteer and boot to kernel
No, I did not try those experiments. […]
Can you please give it a try to see if disabling half channel works as expected on volteer? At least that will give us confidence in setting of DISABLE_BOTH_DIMMS.
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40061/3//COMMIT_MSG@13 PS3, Line 13: build volteer and boot to kernel
Can you please give it a try to see if disabling half channel works as expected on volteer? At least […]
Sure, I will it a try and update.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD ......................................................................
Patch Set 5: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40061/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40061/5//COMMIT_MSG@12 PS5, Line 12: "DisableDimmCh#" UPD Please add a dot/period at the end of sentences.
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40061
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD. ......................................................................
soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD.
This change updates memory configuration on Tiger Lake Platform to replace "Reserved9" with "DisableDimmCh#" UPD in init_spd_upds(). For reference https://review.coreboot.org/c/coreboot/+/39797 added "DisableDimmCh#" UPD.
BUG=b:150357377 BRANCH=none TEST= build volteer and boot to kernel
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40061/6
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD. ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40061/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40061/5//COMMIT_MSG@12 PS5, Line 12: "DisableDimmCh#" UPD
Please add a dot/period at the end of sentences.
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD. ......................................................................
Patch Set 6: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD. ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40061/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40061/6//COMMIT_MSG@14 PS6, Line 14: BUG=b:150357377 BTW, this bug is not correct anymore.
Furquan Shaikh has uploaded a new patch set (#7) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD. ......................................................................
soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD.
This change updates memory configuration on Tiger Lake Platform to replace "Reserved9" with "DisableDimmCh#" UPD in init_spd_upds(). For reference https://review.coreboot.org/c/coreboot/+/39797 added "DisableDimmCh#" UPD.
BUG=b:152000235 BRANCH=none TEST= build volteer and boot to kernel
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40061/7
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD. ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40061/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40061/6//COMMIT_MSG@14 PS6, Line 14: BUG=b:150357377
BTW, this bug is not correct anymore.
Done
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD. ......................................................................
soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD.
This change updates memory configuration on Tiger Lake Platform to replace "Reserved9" with "DisableDimmCh#" UPD in init_spd_upds(). For reference https://review.coreboot.org/c/coreboot/+/39797 added "DisableDimmCh#" UPD.
BUG=b:152000235 BRANCH=none TEST= build volteer and boot to kernel
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40061 Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Nick Vaccaro nvaccaro@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 864f079..bd9a4ff 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -40,45 +40,53 @@ static void init_spd_upds(FSP_M_CONFIG *mem_cfg, int channel, uintptr_t spd_dimm0, uintptr_t spd_dimm1) { - mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1); + uint8_t dimm_cfg = get_dimm_cfg(spd_dimm0, spd_dimm1);
switch (channel) { case 0: + mem_cfg->DisableDimmCh0 = dimm_cfg; mem_cfg->MemorySpdPtr00 = spd_dimm0; mem_cfg->MemorySpdPtr01 = spd_dimm1; break;
case 1: + mem_cfg->DisableDimmCh1 = dimm_cfg; mem_cfg->MemorySpdPtr02 = spd_dimm0; mem_cfg->MemorySpdPtr03 = spd_dimm1; break;
case 2: + mem_cfg->DisableDimmCh2 = dimm_cfg; mem_cfg->MemorySpdPtr04 = spd_dimm0; mem_cfg->MemorySpdPtr05 = spd_dimm1; break;
case 3: + mem_cfg->DisableDimmCh3 = dimm_cfg; mem_cfg->MemorySpdPtr06 = spd_dimm0; mem_cfg->MemorySpdPtr07 = spd_dimm1; break;
case 4: + mem_cfg->DisableDimmCh4 = dimm_cfg; mem_cfg->MemorySpdPtr08 = spd_dimm0; mem_cfg->MemorySpdPtr09 = spd_dimm1; break;
case 5: + mem_cfg->DisableDimmCh5 = dimm_cfg; mem_cfg->MemorySpdPtr10 = spd_dimm0; mem_cfg->MemorySpdPtr11 = spd_dimm1; break;
case 6: + mem_cfg->DisableDimmCh6 = dimm_cfg; mem_cfg->MemorySpdPtr12 = spd_dimm0; mem_cfg->MemorySpdPtr13 = spd_dimm1; break;
case 7: + mem_cfg->DisableDimmCh7 = dimm_cfg; mem_cfg->MemorySpdPtr14 = spd_dimm0; mem_cfg->MemorySpdPtr15 = spd_dimm1; break;
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD. ......................................................................
Patch Set 8:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2100 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2099 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2098
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Furquan Shaikh (Code Review)
-
Nick Vaccaro (Code Review)
-
Paul Menzel (Code Review)
-
Srinidhi N Kaushik (Code Review)
-
Wonkyu Kim (Code Review)