Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
Patch Set 1:
(2 comments)
Can you please remove the dependency of this CL on https://review.coreboot.org/c/coreboot/+/40026. Fixing of DisableDimmChX is not dependent on that CL.
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... File src/soc/intel/tigerlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... PS1, Line 43: mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1);
With this CL being merged https://review.coreboot.org/c/coreboot/+/39797.. […]
Woops. That is right. FSP UPD header change has to go in along with change in coreboot that was relying on any of the reserved UPDs. Thanks for fixing this!
https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... PS1, Line 234: mem_cfg->MrcSafeConfig = 0x1; Can you please push this as a separate change as it is required after 2527 lands.