[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resource

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )

Change subject: src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resource
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Patch Set 8:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@15 
PS3, Line 15: range as cacheable (+ reserved) and other ranges as reserve alone.
> @Aaron, i guess you meant this https://review.coreboot. […]

That is what I meant. If we've already utilized TSEG from early mtrr solution and it was marked cacheable we get the speed up. After that we finalize our MTRR solution for boot. Looks like we do what I noted when !CONFIG(USE_INTEL_FSP_MP_INIT). When CONFIG(USE_INTEL_FSP_MP_INIT) = y then that assumption breaks down looking at post_cpus_init() in src/soc/intel/common/block/cpu/mp_init.c