Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41898 )
Change subject: soc/amd/picasso: solve MTRRs only from 4GiB and below ......................................................................
Patch Set 4: Code-Review+1
Patch Set 4:
I cherry-picked the 3 MTRR changes and the Mandolin support on top of current coreboot master and rebuilt FSP, but first ramstage seems to crash (just stops and bootblock is rung again) and the second time it failed with "FspMemoryInit returned 0x80000003". Without the 3 patches, but with the freshly built FSP coreboot hangs when running the VBIOS, so I'm reasonably sure that I'm running with the MTRR changes on the FSP side
It sounded like there was something goofed with yesterday's CQ ordering and many people were seeing problems. So hopefully if you give it another try it'll be OK. I did a repo sync Saturday morning and checked it on Mandolin. I rebased these 3 changes on top of 524962 and cherry-picked CB:33772. I'm not seeing the problems you're reporting. Also FWIW I verified the MTRRs are unmodified during the two FSP calls.