Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32045
Change subject: soc/intel/skylake: Add devicetree options for PEG ......................................................................
soc/intel/skylake: Add devicetree options for PEG
List of options for each port: - PegMaxLinkSpeed - PegMaxLinkWidth - PegPowerDownUnusedLanes - PegGen3EqPh2Enable
To enable or disable the corresponding PEG root port you need to add to the devicetree.cb:
device pci 01.0 on end # enable PEG0 root port device pci 01.1 off end # do not configure PEG1
If PEG port is not defined in the devicetree, it will be disabled in FSP.
Change-Id: I23708f7060edf08739adf61fe61a419329907563 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 4 files changed, 100 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32045/1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 53094b1..de476ff 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -258,6 +258,10 @@ bool default n
+config MAX_PEG_PORTS + int + default 3 + config MAX_ROOT_PORTS int default 24 if PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a8ee064..1f0e2f4 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -214,6 +214,42 @@ */
/* + * PEG max link speed + * 0: Maximum possible link speed, + * which is set in FSP. + * 1: Gen1 link speed + * 2: Gen2 link speed + * 3: Gen3 link speed + */ + u8 PegMaxLinkSpeed[CONFIG_MAX_PEG_PORTS]; + + /* + * PEG Max Link Width + * 0: Maximum possible link width: + * x16 for PEG0, + * x8 for PEG1, + * x4 for PEG2. + * 1: x1 + * 2: x4, only for PEG0 and PEG1 + * 3: x8, only for PEG0 + */ + u8 PegMaxLinkWidth[CONFIG_MAX_PEG_PORTS]; + + /* + * Power down unused lanes on PEG + * 0: No power saving + * 1: Power down unused lanes + */ + u8 PegPowerDownUnusedLanes[CONFIG_MAX_PEG_PORTS]; + + /* + * Phase2 EQ enable on the PEG + * 0: Disable phase 2 + * 1: Enable phase 2 + */ + u8 PegGen3EqPh2Enable[CONFIG_MAX_PEG_PORTS]; + + /* * Enable/Disable Root Port * 0: Disable Root Port * 1: Enable Root Port diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index f695794..d59c800 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -37,6 +37,13 @@ #define SA_DEVFN_ROOT _SA_DEVFN(ROOT) #define SA_DEV_ROOT _SA_DEV(ROOT)
+#define SA_DEV_SLOT_PEG 0x01 +#define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func) +#define SA_DEV_PEG(func) dev_find_slot(0, SA_DEVFN_PEG(func)) +#define SA_DEV_PEG0 SA_DEV_PEG(0) +#define SA_DEV_PEG1 SA_DEV_PEG(1) +#define SA_DEV_PEG2 SA_DEV_PEG(2) + #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD _SA_DEVFN(IGD) #define SA_DEV_IGD _SA_DEV(IGD) diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index f38a775..b963d17 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -202,6 +202,58 @@ m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; }
+static void soc_peg_init_params(FSP_M_CONFIG *m_cfg, + FSP_M_TEST_CONFIG *m_t_cfg, + const struct soc_intel_skylake_config *config) +{ + const struct device *dev; + /* + * To enable or disable the corresponding PEG root port you need to + * add to the devicetree.cb: + * + * device pci 01.0 on end # enable PEG0 root port + * device pci 01.1 off end # do not configure PEG1 + * + * If PEG port is not defined in the device tree, it will be disabled + * in FSP + */ + dev = SA_DEV_PEG0; /* PEG 0:1:0 */ + if (!dev || !dev->enabled) + m_cfg->Peg0Enable = 0; + else if (dev->enabled) { + m_cfg->Peg0Enable = dev->enabled; + m_cfg->Peg0MaxLinkSpeed = config->PegMaxLinkSpeed[0]; + m_cfg->Peg0MaxLinkWidth = config->PegMaxLinkWidth[0]; + m_cfg->Peg0PowerDownUnusedLanes = + config->PegPowerDownUnusedLanes[0]; + m_t_cfg->Peg0Gen3EqPh2Enable = config->PegGen3EqPh2Enable[0]; + } + + dev = SA_DEV_PEG1; /* PEG 0:1:1 */ + if (!dev || !dev->enabled) + m_cfg->Peg1Enable = 0; + else if (dev->enabled) { + m_cfg->Peg1Enable = dev->enabled; + m_cfg->Peg1MaxLinkSpeed = config->PegMaxLinkSpeed[1]; + m_cfg->Peg1MaxLinkWidth = config->PegMaxLinkWidth[1]; + m_cfg->Peg1PowerDownUnusedLanes = + config->PegPowerDownUnusedLanes[1]; + m_t_cfg->Peg1Gen3EqPh2Enable = config->PegGen3EqPh2Enable[1]; + } + + dev = SA_DEV_PEG0; /* PEG 0:1:2 */ + if (!dev || !dev->enabled) + m_cfg->Peg2Enable = 0; + else if (dev->enabled) { + m_cfg->Peg2Enable = dev->enabled; + m_cfg->Peg2MaxLinkSpeed = config->PegMaxLinkSpeed[2]; + m_cfg->Peg2MaxLinkWidth = config->PegMaxLinkWidth[2]; + m_cfg->Peg2PowerDownUnusedLanes = + config->PegPowerDownUnusedLanes[2]; + m_t_cfg->Peg2Gen3EqPh2Enable = config->PegGen3EqPh2Enable[2]; + } +} + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_skylake_config *config) { @@ -254,6 +306,7 @@ config = dev->chip_info;
soc_memory_init_params(m_cfg, config); + soc_peg_init_params(m_cfg, m_t_cfg, config);
/* Skip creating Management Engine MBP HOB */ m_t_cfg->SkipMbpHob = 0x01;