Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )
Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@10 PS3, Line 10: that one can perform SMRAM relocation faster.
But this was already happening.
yes, it just to only make TSEG range notthe entire stolen range cacheable, i will update the commit msg to make it clear
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@15 PS3, Line 15: range as cacheable (+ reserved) and other ranges as reserve alone.
What's the motivation? If the order of operations is maintained (us doing mpinit w/ smm relocation e […]
Do you mean to remove TSEG region reservation like below ? I could see if we are not marking this TSEG range reserved that PCI enumeration is giving that region to other device as BAR and creating problem (like i saw TSEG region has given to SATA and system is keep on rebooting or its given to IGD and accessing IGD region is causing MCE)
+#if 0 /* TSEG -> BGSM */ base_k = sa_map_values[SA_TSEG_REG]; size_k = sa_map_values[SA_BGSM_REG] - base_k; reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); - +#endif