Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )
Change subject: src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resource ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@15 PS3, Line 15: range as cacheable (+ reserved) and other ranges as reserve alone.
When CONFIG(USE_INTEL_FSP_MP_INIT) = y then that assumption breaks down looking at post_cpus_init […]
Also Aaron, as you brought this point, i could ask your feedback about how you would recommend the flow when user selects USE_INTEL_FSP_MP_INIT, in those cases, CB don't run mp init earlier w/ smm and FSP-S will bring APs up. But after FSP-S done and control comes back, we might need to run init_cpus() to bring those AP in coreboot context so it can run post_cpus_init with same assumption.
Can we do something like this? 1. Do init_cpus() after FSP-S exit if USE_INTEL_FSP_MP_INIT is selected => to bring all cores back into cb context 2. Remove USE_INTEL_FSP_MP_INIT check inside post_cpus_init() as we would like all cores to have MTRR updated based on DRAM snapshot else i could see it still has old MTRR snapshot (before DRAM) after booting to OS incase USE_INTEL_FSP_MP_INIT is selected