[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: update memory cfg for Tiger Lake

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )

Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... 
File src/soc/intel/tigerlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... 
PS1, Line 43: 	mem_cfg->Reserved9[channel] = get_dimm_cfg(spd_dimm0, spd_dimm1);
With this CL being merged https://review.coreboot.org/c/coreboot/+/39797.. we were hitting array out of bound since Reserved9 is only 2 elements now.