Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49136 )
Change subject: mb/intel/adlrvp: Fix wrong comments and typo ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/49136/1/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49136/1/src/mainboard/intel/adlrvp/... PS1, Line 72: register "PcieClkSrcUsage[0]" = "0x40" As far as I understand it, this configures PCH CLKSRC 0 to be used for CPU PCIe RP 1.
https://review.coreboot.org/c/coreboot/+/49136/1/src/mainboard/intel/adlrvp/... PS1, Line 75: register "PcieClkSrcUsage[3]" = "0x41" Same here, as far as I understand it, this configures PCH CLKSRC 3 to be used for CPU PCIe RP 2.
https://review.coreboot.org/c/coreboot/+/49136/1/src/mainboard/intel/adlrvp/... PS1, Line 76: register "PcieClkSrcUsage[4]" = "0x42" Same here, as far as I understand it, this configures PCH CLKSRC 4 to be used for CPU PCIe RP 3.