3 comments:
File src/mainboard/intel/adlrvp/devicetree.cb:
Patch Set #1, Line 72: register "PcieClkSrcUsage[0]" = "0x40"
As far as I understand it, this configures PCH CLKSRC 0 to be used for CPU PCIe RP 1.
Patch Set #1, Line 75: register "PcieClkSrcUsage[3]" = "0x41"
Same here, as far as I understand it, this configures PCH CLKSRC 3 to be used for CPU PCIe RP 2.
Patch Set #1, Line 76: register "PcieClkSrcUsage[4]" = "0x42"
Same here, as far as I understand it, this configures PCH CLKSRC 4 to be used for CPU PCIe RP 3.
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