Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31123 )
Change subject: WIP: bootmem: add new memory type for BL31 ......................................................................
Patch Set 6:
(3 comments)
Is there any way to verify this? I can only test this on a mt8173 device I have, but each platform uses different approach to setup its reserved range.. (Or maybe it's not a good idea to break compatibility?)
Review is enough... we aren't *that* afraid of breaking things in coreboot, and this change isn't crazy hard to grok. Stifling all innovation because people are too afraid of breaking old junk isn't great either.
https://review.coreboot.org/#/c/31123/6/src/soc/cavium/cn81xx/soc.c File src/soc/cavium/cn81xx/soc.c:
https://review.coreboot.org/#/c/31123/6/src/soc/cavium/cn81xx/soc.c@332 PS6, Line 332: BM_MEM_BL31); Rather than doing this in every SoC this should be added to arm64's bootmem_arch_ranges(). You can use DECLARE_OPTIONAL_REGION(bl31) and test for _bl31_size to be non-zero before adding it so that platform with some weird special requirements have an out.
https://review.coreboot.org/#/c/31123/6/src/soc/nvidia/tegra210/soc.c File src/soc/nvidia/tegra210/soc.c:
https://review.coreboot.org/#/c/31123/6/src/soc/nvidia/tegra210/soc.c@53 PS6, Line 53: bootmem_add_range(begin * KiB * KiB, size * KiB * KiB, type); This is one of those examples where it's probably a good idea to have the platform handle it separately and not put it in memlayout.
https://review.coreboot.org/#/c/31123/6/src/soc/rockchip/rk3399/soc.c File src/soc/rockchip/rk3399/soc.c:
https://review.coreboot.org/#/c/31123/6/src/soc/rockchip/rk3399/soc.c@41 PS6, Line 41: bootmem_add_range(TZRAM_BASE, TZRAM_SIZE, BM_MEM_BL31); FYI, the range here (that should now be hardcoded in memlayout) is [0x0:0x100000] (from https://github.com/ARM-software/arm-trusted-firmware/blob/master/plat/rockch...).