Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47183 )
Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47183/1/src/soc/intel/jasperlake/el... File src/soc/intel/jasperlake/elog.c:
https://review.coreboot.org/c/coreboot/+/47183/1/src/soc/intel/jasperlake/el... PS1, Line 43: { PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, : { PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 }, : { PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, : { PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 },
Nit: JSL has only 8 PCIe root ports. I see that the condition in line 49 ensures that that. […]
They're defined in soc/pci_devs.h as the first four functions in 00:1d; maybe a different processor SKU could have them and then the mainboard would only need to change the Kconfig.