Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 134:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/13/src/mainboard/acer/aspire_... PS13, Line 150: # register "PcieRpEnable[6]" = "1"
Port 7 actually backs SATA. Port 8 is NGFF.
May not be correct.
PCIe/SATA/USB page of the schematics places SSD/SATA on RP7/SATA0 and SSD/PCIE on RP8/SATA1a. HDD1 is on RP11/SATA1b and ODD on RP12/SATA2.
SSD/SATA and SSD/PCIE both lead to mSATA.
The vendor BIOS disables and hides SATA0 settings behind gray-out (perhaps only because no device is present), but unequivocally enables RP7. I found some settings in a config.xml extracted by Intel FIT from a vendor update and SPI dump that may clear this up.
RP7/SATA0: GPIO RP8/SATA1: PCIe RP11/SATA1: SATA RP12/SATA2: SATA
Ports 1-4: 1x4 Ports 5-8: 2x2 Ports 9-12: 4x1
It appears to me that there is an mSATA/NGFF port on RP7+RP8 and no SATA0.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 53: 0
Done
RP7/SATA0 is muxed with RP8/SATA1 to make an x2 port for mSATA. However, as noted above, it is SATA0 with RP8 that the schematics show wired to mSATA.
https://review.coreboot.org/c/coreboot/+/35523/62/src/mainboard/acer/aspire_... PS62, Line 232: [PchSerialIoIndexUart2] = PchSerialIoDisabled,
Must UART pins be programmed in bootblock then?
Should CONSOLE_SERIAL be enabled? If it is an LPSS UART and in-memory, should the coreboot + payload log be able to be read after boot?
https://review.coreboot.org/c/coreboot/+/35523/119/src/mainboard/acer/aspire... File src/mainboard/acer/aspire_vn7_572g/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/35523/119/src/mainboard/acer/aspire... PS119, Line 68: # TODO: register "DspEndpointDmic" = "3"
The vendor is using this UPD to enable the microphone as none of the HDA pin_cfgs address a micropho […]
The microphone is attached to the webcam and the schematics assert that the pins are "reserved for SST." It does seem as though it could be an [OS issue](https://github.com/takaswie/sound/commit/df1fceacb24853d79f41a1dd717b32ab08f...). That commit apparently landed in -next, so I'll wait and see. However, it may still need an HDA pin_cfg.