Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40229 )
Change subject: sb/intel/bd82x6x/sata: Don't write RO register ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40229/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40229/1//COMMIT_MSG@7 PS1, Line 7: sb/intel/bd82x6x/sata: Don't write RO register Ooops, now that I see it again, it's actually not trying to write the read-only part (interrupt pin would be ro, interrupt line is r/w)... Of course there is a(nother) reason I dropped the code:
The interrupt line registers are configured in a central place, pch_pirq_init() in `lpc.c`, according to the PIRQ configuration. Hardcoding values here makes no sense.
https://review.coreboot.org/c/coreboot/+/40229/1/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/sata.c:
https://review.coreboot.org/c/coreboot/+/40229/1/src/southbridge/intel/bd82x... PS1, Line 63: pci_write_config8(dev, INTR_LN, 0x0a); Please also remove this and the definition of INTR_LN in `pch.h`.