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2 comments:

• Commit Message:

  • Patch Set #1, Line 7: sb/intel/bd82x6x/sata: Don't write RO register

    Ooops, now that I see it again, it's actually not trying to write the
    read-only part (interrupt pin would be ro, interrupt line is r/w)...
    Of course there is a(nother) reason I dropped the code:

    The interrupt line registers are configured in a central place,
    pch_pirq_init() in `lpc.c`, according to the PIRQ configuration.
    Hardcoding values here makes no sense.

• File src/southbridge/intel/bd82x6x/sata.c:

  • Patch Set #1, Line 63: pci_write_config8(dev, INTR_LN, 0x0a);

    Please also remove this and the definition of INTR_LN in `pch.h`.

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