[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48449 )

Change subject: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8
......................................................................

mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8

1. Make CLKSRC -> 7 and CLKREQ -> 6
2. CLK 6 is using free running CLK
3. Make LAN CLK 7 as unused as GbE is disable

TEST=Able to detect PCIE SD card on 0x1 slot.

Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48449
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: V Sowmya 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/adlrvp/devicetree.cb
1 file changed, 5 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  V Sowmya: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index daf6ed1..12cd475 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -51,11 +51,11 @@
    register "PcieClkSrcUsage[5]" = "0x5"
    register "PcieRpClkReqDetect[5]" = "1"

-	# Enable PCH PCIE RP 8 using free running CLK (0x80)
+	# Enable PCH PCIE RP 8 using CLK 6
    register "PcieRpEnable[7]" = "1"
-	register "PcieClkSrcClkReq[7]" = "7"
-	register "PcieClkSrcUsage[7]" = "0x80"
-	register "PcieRpClkReqDetect[7]" = "1"
+	register "PcieClkSrcClkReq[7]" = "6" # CLKSRC -> 7 and CLKREQ -> 6
+	register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK
+	register "PcieRpClkReqDetect[6]" = "1"

# Enable PCH PCIE RP 9 using CLK 1
    register "PcieRpEnable[8]" = "1"
@@ -76,7 +76,7 @@
    register "PcieClkSrcUsage[4]" = "0x42"

# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
-	register "PcieClkSrcUsage[6]" = "0xff"
+	register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"

register "SataSalpSupport" = "1"