Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48449 )
Change subject: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 ......................................................................
mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8
1. Make CLKSRC -> 7 and CLKREQ -> 6 2. CLK 6 is using free running CLK 3. Make LAN CLK 7 as unused as GbE is disable
TEST=Able to detect PCIE SD card on 0x1 slot.
Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 4 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/48449/1
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index daf6ed1..306fce7 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -51,11 +51,10 @@ register "PcieClkSrcUsage[5]" = "0x5" register "PcieRpClkReqDetect[5]" = "1"
- # Enable PCH PCIE RP 8 using free running CLK (0x80) + # Enable PCH PCIE RP 8 using CLK 6 register "PcieRpEnable[7]" = "1" - register "PcieClkSrcClkReq[7]" = "7" - register "PcieClkSrcUsage[7]" = "0x80" - register "PcieRpClkReqDetect[7]" = "1" + register "PcieClkSrcClkReq[7]" = "6" # CLKSRC -> 7 and CLKREQ -> 6 + register "PcieClkSrcUsage[6]" = "0x80"
# Enable PCH PCIE RP 9 using CLK 1 register "PcieRpEnable[8]" = "1" @@ -76,7 +75,7 @@ register "PcieClkSrcUsage[4]" = "0x42"
# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below - register "PcieClkSrcUsage[6]" = "0xff" + register "PcieClkSrcUsage[7]" = "0xff"
register "SataSalpSupport" = "1"
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48449
to look at the new patch set (#2).
Change subject: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 ......................................................................
mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8
1. Make CLKSRC -> 7 and CLKREQ -> 6 2. CLK 6 is using free running CLK 3. Make LAN CLK 7 as unused as GbE is disable
TEST=Able to detect PCIE SD card on 0x1 slot.
Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/48449/2
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48449
to look at the new patch set (#3).
Change subject: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 ......................................................................
mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8
1. Make CLKSRC -> 7 and CLKREQ -> 6 2. CLK 6 is using free running CLK 3. Make LAN CLK 7 as unused as GbE is disable
TEST=Able to detect PCIE SD card on 0x1 slot.
Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/48449/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48449 )
Change subject: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 ......................................................................
Patch Set 3: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/48449/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48449/3/src/mainboard/intel/adlrvp/... PS3, Line 57: 0x80 `PCIE_CLK_FREE`
https://review.coreboot.org/c/coreboot/+/48449/3/src/mainboard/intel/adlrvp/... PS3, Line 79: 0xff `PCIE_CLK_NOTUSED`
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48449 )
Change subject: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48449/3/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48449/3/src/mainboard/intel/adlrvp/... PS3, Line 57: 0x80
`PCIE_CLK_FREE`
Ack
https://review.coreboot.org/c/coreboot/+/48449/3/src/mainboard/intel/adlrvp/... PS3, Line 79: 0xff
`PCIE_CLK_NOTUSED`
Ack
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48449
to look at the new patch set (#4).
Change subject: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 ......................................................................
mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8
1. Make CLKSRC -> 7 and CLKREQ -> 6 2. CLK 6 is using free running CLK 3. Make LAN CLK 7 as unused as GbE is disable
TEST=Able to detect PCIE SD card on 0x1 slot.
Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/48449/4
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48449 )
Change subject: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 ......................................................................
Patch Set 5:
@Tim: Can you please take a look ?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48449 )
Change subject: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 ......................................................................
Patch Set 5: Code-Review+2
V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48449 )
Change subject: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 ......................................................................
Patch Set 5: Code-Review+2
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48449 )
Change subject: mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8 ......................................................................
mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8
1. Make CLKSRC -> 7 and CLKREQ -> 6 2. CLK 6 is using free running CLK 3. Make LAN CLK 7 as unused as GbE is disable
TEST=Able to detect PCIE SD card on 0x1 slot.
Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48449 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: V Sowmya v.sowmya@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified V Sowmya: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index daf6ed1..12cd475 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -51,11 +51,11 @@ register "PcieClkSrcUsage[5]" = "0x5" register "PcieRpClkReqDetect[5]" = "1"
- # Enable PCH PCIE RP 8 using free running CLK (0x80) + # Enable PCH PCIE RP 8 using CLK 6 register "PcieRpEnable[7]" = "1" - register "PcieClkSrcClkReq[7]" = "7" - register "PcieClkSrcUsage[7]" = "0x80" - register "PcieRpClkReqDetect[7]" = "1" + register "PcieClkSrcClkReq[7]" = "6" # CLKSRC -> 7 and CLKREQ -> 6 + register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK + register "PcieRpClkReqDetect[6]" = "1"
# Enable PCH PCIE RP 9 using CLK 1 register "PcieRpEnable[8]" = "1" @@ -76,7 +76,7 @@ register "PcieClkSrcUsage[4]" = "0x42"
# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below - register "PcieClkSrcUsage[6]" = "0xff" + register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
register "SataSalpSupport" = "1"
-
Subrata Banik (Code Review) -
Tim Wawrzynczak (Code Review)
-
V Sowmya (Code Review)