Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )
Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@58 PS3, Line 58: MTRR: WB selected as default type.
I see. If WRCOMB type is removed, it means we've ran out of variabke MTRRs, which is not good.
Looking at the log it appears that below MTRR are also remain unclaimed in BIOS and OS space. so we are not running completely out
Coreboot log: 0x0000000000000000: PHYBASE6 0x0000000000000000: PHYMASK6: Disabled 0x0000000000000000: PHYBASE7 0x0000000000000000: PHYMASK7: Disabled 0x0000000000000000: PHYBASE8 0x0000000000000000: PHYMASK8: Disabled 0x0000000000000000: PHYBASE9 0x0000000000000000: PHYMASK9: Disabled
Chrome OS log:
[ 0.039794] MTRR variable ranges enabled: [ 0.043754] 0 base 000077000000 mask 3FFFFF000000 uncachable [ 0.049512] 1 base 000078000000 mask 3FFFFE000000 uncachable [ 0.055269] 2 base 00007A000000 mask 3FFFFF000000 uncachable [ 0.061027] 3 base 00007B800000 mask 3FFFFF800000 uncachable [ 0.066792] 4 base 00007C000000 mask 3FFFFC000000 uncachable [ 0.072550] 5 base 000080000000 mask 3FFF80000000 uncachable [ 0.078309] 6 disabled [ 0.080802] 7 disabled [ 0.083295] 8 disabled [ 0.085788] 9 disabled
So, is there anything inside the 0x77000000 - 0x7b000000 memory range that needs to be marked as uncachable?
ME stolen memory which is used for HOST communication with security controller which i don't should be part of cacheable range, Also other reserved range if any like Tracehub etc no point of making at part of cachaable just to avoid MTRR running issue.