Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47049 )
Change subject: mb/google/volteer: Skip TPM detection except on SPI ......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/c/coreboot/+/47049/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47049/7//COMMIT_MSG@14 PS7, Line 14: The I2C drivers do not support : being accessed early in ramstage So, shouldn't we fix the I2C drivers in that case?
https://review.coreboot.org/c/coreboot/+/47049/7//COMMIT_MSG@16 PS7, Line 16: I2C : controller base address It is because the I2C driver seems to be assuming that the BAR is allocated before I2C initialization. However, for the TPM access case, that assumption doesn't hold and hence the driver behavior needs to be fixed.
https://review.coreboot.org/c/coreboot/+/47049/7//COMMIT_MSG@19 PS7, Line 19: can be made to support : longer interrupts Is that the default for Dauntless firmware i.e. will it always support longer interrupts without an additional register write? Or is the new interrupt signalling mode supposed to guarantee that 100us+ pulse would be seen on the interrupt line without any additional configuration from the host?
In my opinion that should be the default. But, is this already captured somewhere and implemented in that way?
https://review.coreboot.org/c/coreboot/+/47049/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/47049/7/src/mainboard/google/voltee... PS7, Line 103: it will use long pulses by default, or use the interrupt line in : * a different way altogether Which one is it? Is it tracked in some bug?