[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: Correct SPI FIFO size check

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37721 )

Change subject: soc/amd/common: Correct SPI FIFO size check
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Patch Set 1: Code-Review-2
> Patch Set 1: Code-Review+2
> > Patch Set 1: Code-Review-1
> > Ideally amd/block/spi would work with hudson too.
>
> Why would soc/amd code apply to southbridge/amd chips?  Isn't it ok to draw a line and say that the soc blocks will only support chips in the soc directory?

My -1 is because of not using the introduced to SPI subsystem that tells command byte will not consume FIFO. Giving this -2 and hoping Furquan will comment as he probably nows the reasoning best why the flag was added.