Patch Set 1: Code-Review+2

Patch Set 1: Code-Review-1
Ideally amd/block/spi would work with hudson too.

Why would soc/amd code apply to southbridge/amd chips? Isn't it ok to draw a line and say that the soc blocks will only support chips in the soc directory?

My -1 is because of not using the introduced to SPI subsystem that tells command byte will not consume FIFO. Giving this -2 and hoping Furquan will comment as he probably nows the reasoning best why the flag was added.

Patch set 1:Code-Review -2

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Gerrit-Project: coreboot
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Gerrit-Change-Id: Ica2ca514deea401c9c5396913087e07a12ab3cf3
Gerrit-Change-Number: 37721
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