[coreboot-gerrit] Change in ...coreboot[master]: vc/amd/agesa/f14: Add missing break statement

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32180 )

Change subject: vc/amd/agesa/f14: Add missing break statement
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vc/amd/agesa/f14: Add missing break statement

We do not want to ASSERT(FALSE).

Found-by: Coverity Scan, CID 1241850 (MISSING_BREAK)
Signed-off-by: Jacob Garber 
Change-Id: Ia08bb519cdb5ef5d2a79898706c7fac7e58adf3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32180
Tested-by: build bot (Jenkins) 
Reviewed-by: HAOUAS Elyes 
Reviewed-by: Kyösti Mälkki 
---
M src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, approved
  HAOUAS Elyes: Looks good to me, but someone else must approve

diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
index 7fb195d..daf529c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
@@ -792,6 +792,7 @@
         break;
       case AccessS3SaveWidth32:
         RegValue = *(UINT32 *) Value;
+	break;
       default:
         ASSERT (FALSE);
       }