Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32180
Change subject: vc/amd/agesa/f14: Add missing break statement ......................................................................
vc/amd/agesa/f14: Add missing break statement
We do not want to ASSERT(FALSE).
Found-by: Coverity Scan, CID 1241850 (MISSING_BREAK) Signed-off-by: Jacob Garber jgarber1@ualberta.ca Change-Id: Ia08bb519cdb5ef5d2a79898706c7fac7e58adf3f --- M src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/32180/1
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c index 7fb195d..daf529c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c @@ -792,6 +792,7 @@ break; case AccessS3SaveWidth32: RegValue = *(UINT32 *) Value; + break; default: ASSERT (FALSE); }
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32180 )
Change subject: vc/amd/agesa/f14: Add missing break statement ......................................................................
Patch Set 1: Code-Review+1
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32180 )
Change subject: vc/amd/agesa/f14: Add missing break statement ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32180 )
Change subject: vc/amd/agesa/f14: Add missing break statement ......................................................................
vc/amd/agesa/f14: Add missing break statement
We do not want to ASSERT(FALSE).
Found-by: Coverity Scan, CID 1241850 (MISSING_BREAK) Signed-off-by: Jacob Garber jgarber1@ualberta.ca Change-Id: Ia08bb519cdb5ef5d2a79898706c7fac7e58adf3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32180 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c index 7fb195d..daf529c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c @@ -792,6 +792,7 @@ break; case AccessS3SaveWidth32: RegValue = *(UINT32 *) Value; + break; default: ASSERT (FALSE); }
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HAOUAS Elyes (Code Review) -
Jacob Garber (Code Review)
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Kyösti Mälkki (Code Review)