Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50996 )
Change subject: mb/adlrvp: Fix DDR5 Boot issue ......................................................................
Patch Set 13:
(13 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50996/comment/d7719f84_582a4508 PS4, Line 7: Boot
boot
Ack
https://review.coreboot.org/c/coreboot/+/50996/comment/3b103f9a_dfe432e2 PS4, Line 12: implemention
implementation
Ack
Commit Message:
https://review.coreboot.org/c/coreboot/+/50996/comment/d4caf477_05e02d0a PS6, Line 7: Boot
boot
Ack
https://review.coreboot.org/c/coreboot/+/50996/comment/b79e2f6f_6349bb51 PS6, Line 7: mb/adlrvp
mb/intel/adlrvp
Ack
https://review.coreboot.org/c/coreboot/+/50996/comment/d1c2554b_3087b357 PS6, Line 7: Fix DDR5 Boot issue
Pass DIMM slave address to FSP to fix DDR5 boot
Ack
https://review.coreboot.org/c/coreboot/+/50996/comment/d79286c3_ad55eed0 PS6, Line 9: DDR5 boot is broken due to reading of spd data : via SMBus through coreboot
Since the beginning, or did some commit introduce the regression.
Ack
https://review.coreboot.org/c/coreboot/+/50996/comment/8f8df221_148ed1d5 PS6, Line 9: Currently, DDR5 boot is broken due to reading of spd data : via SMBus through coreboot. This implementation requires study : of spd5 architecture and is currently Work In Progress.
Please note, what problem is seen, like: […]
Ack
https://review.coreboot.org/c/coreboot/+/50996/comment/d7456ac5_0f69b3b6 PS6, Line 12: implemention
implementation
Ack
File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/50996/comment/cf5fa065_b5705e74 PS6, Line 34: int
unsigned int
Ack
https://review.coreboot.org/c/coreboot/+/50996/comment/821f3fc3_a50cbaa8 PS6, Line 61: CONFIG_MRC_CHANNEL_WIDTH ;
Please remove the space before the ;.
Ack
File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/50996/comment/b3781482_cad29fb3 PS8, Line 63: mupd->FspmConfig.SpdAddressTable[i] = spd_array[i];
I just noticed that the `phys_to_mrc_map` array for DDR5 looks odd. […]
Ack
File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/50996/comment/dccd771b_652fa9b6 PS9, Line 58: &mupd->FspmConfig
check this CL https://review.coreboot. […]
Ack
File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/50996/comment/00b27dcd_e1940ad0 PS10, Line 58: half_populated
No Subrata, since we are passing the address at the exact array element where the DIMM is to be foun […]
Ack