Attention is currently required from: Bora Guvendik, Furquan Shaikh, Selma Bensaid, Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik.
13 comments:
Commit Message:
boot
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Patch Set #4, Line 12: implemention
implementation
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Commit Message:
boot
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Patch Set #6, Line 7: mb/adlrvp
mb/intel/adlrvp
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Patch Set #6, Line 7: Fix DDR5 Boot issue
Pass DIMM slave address to FSP to fix DDR5 boot
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DDR5 boot is broken due to reading of spd data
via SMBus through coreboot
Since the beginning, or did some commit introduce the regression.
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Currently, DDR5 boot is broken due to reading of spd data
via SMBus through coreboot. This implementation requires study
of spd5 architecture and is currently Work In Progress.
Please note, what problem is seen, like: […]
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Patch Set #6, Line 12: implemention
implementation
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File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
unsigned int
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Patch Set #6, Line 61: CONFIG_MRC_CHANNEL_WIDTH ;
Please remove the space before the ;.
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File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
Patch Set #8, Line 63: mupd->FspmConfig.SpdAddressTable[i] = spd_array[i];
I just noticed that the `phys_to_mrc_map` array for DDR5 looks odd. […]
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File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
Patch Set #9, Line 58: &mupd->FspmConfig
check this CL https://review.coreboot. […]
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File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
Patch Set #10, Line 58: half_populated
No Subrata, since we are passing the address at the exact array element where the DIMM is to be foun […]
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