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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email )
Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 56:
(4 comments)
File src/soc/intel/xeon_sp/gnr/Kconfig:
https://review.coreboot.org/c/coreboot/+/81316/comment/3ab27ef5_fde1abd7 :
PS56, Line 17: select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND
I don't remember if I mentioned this, but it would be great to fix FSP
Intel said this issue is not present on GNR, so this is wrong.
File src/soc/intel/xeon_sp/gnr/chip.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/22926c4c_b20adf3d :
PS56, Line 13: intelblocks
do you need all those headers?
File src/soc/intel/xeon_sp/gnr/cpu.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/38a56b44_816103cb :
PS56, Line 9: common
do you need all those headers?
File src/soc/intel/xeon_sp/gnr/romstage.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/fd504f6a_3c6f6baa :
PS56, Line 5: #include <console/console.h>
do you need all those headers?
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