Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )
Change subject: mb/google/hatch: modify PCIe ports setting for mushu ......................................................................
Patch Set 6:
(8 comments)
Next time, please do two commits.
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@7 PS6, Line 7: mb/google/hatch: modify PCIe ports setting for mushu Please be specific.
Enable dGPU and WLAN devices
Also, I believe Chromium devices use specific prefixes for variants.
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@9 PS6, Line 9: Enabled Enable
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@10 PS6, Line 10: prot port
https://review.coreboot.org/c/coreboot/+/38399/6//COMMIT_MSG@11 PS6, Line 11: Enabled Enable
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 67: 13(x4) Please add a space before (.
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 67: # Enable Root port 13(x4) for dGPU. Please remove the dot at the end.
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 75: # PCIe port 8 reserve for GPU REFCLK … reserve*d* for …
https://review.coreboot.org/c/coreboot/+/38399/6/src/mainboard/google/hatch/... PS6, Line 87: register "PcieClkSrcClkReq[3]" = "3" Shouldn’t this be sorted according to port numbers?