[coreboot-gerrit] Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Patrick Rudolph (Code Review)]

Hello build bot (Jenkins), Michał Żygowski, Angel Pons,  Marcello Sylvester Bauer, Patrick Rudolph, Piotr Król,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44013

to look at the new patch set (#3).

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

arch/x86/smbios: Bump to 3.1

Set the entry point revision to the SMBIOS defined value and bump
version to 3.1. All new fields introduced in 3.1 are already present
and filled with valid data.

Change the type 17 memory speed to MT/s and add a comments to indicate
which unit the fields have.

NEEDS TEST ON ALL PLATFORMS!
SOME BLOBS ADVERTISE MEMORY SPEED IN FALSE UNITS!

Tested on Intel CFL:
The FSP reports memory speed in MT/s even when the comment states
otherwise.

Change-Id: Ieaf876d0297fd12b1ddfe8b3a69704ef03225930
Signed-off-by: Patrick Rudolph 
---
M src/arch/x86/smbios.c
M src/device/dram/ddr3.c
M src/device/dram/ddr4.c
M src/drivers/intel/fsp1_1/romstage.c
M src/include/memory_info.h
M src/include/smbios.h
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/google/cyan/spd/spd.c
M src/mainboard/pcengines/apu1/mainboard.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/northbridge/intel/haswell/raminit.c
M src/soc/amd/common/block/pi/amd_late_init.c
M src/soc/amd/picasso/dmi.c
M src/soc/intel/apollolake/meminit_util_apl.c
M src/soc/intel/apollolake/meminit_util_glk.c
M src/soc/intel/broadwell/romstage/raminit.c
M src/soc/intel/common/smbios.c
M src/soc/intel/denverton_ns/hob_mem.c
M src/soc/intel/icelake/romstage/romstage.c
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
22 files changed, 44 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44013/3