Change in coreboot[master]: smbios: Bump to 3.1

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: smbios: Bump to 3.1
......................................................................

smbios: Bump to 3.1

Set the entry point revision to the SMBIOS defined value and bump
version to 3.1. All new fields introduced in 3.1 are already present
and filled with valid data.

Change-Id: Ieaf876d0297fd12b1ddfe8b3a69704ef03225930
Signed-off-by: Patrick Rudolph 
---
M src/arch/x86/smbios.c
1 file changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44013/1

diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index d7e8747..1f22076 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -1374,7 +1374,7 @@
    memcpy(se->anchor, "_SM_", 4);
    se->length = sizeof(struct smbios_entry);
    se->major_version = 3;
-	se->minor_version = 0;
+	se->minor_version = 1;
    se->max_struct_size = max_struct_size;
    se->struct_count = handle;
    memcpy(se->intermediate_anchor_string, "_DMI_", 5);
@@ -1392,7 +1392,8 @@
    memcpy(se3->anchor, "_SM3_", 5);
    se3->length = sizeof(struct smbios_entry30);
    se3->major_version = 3;
-	se3->minor_version = 0;
+	se3->minor_version = 1;
+	se3->entry_point_rev = 1;

se3->struct_table_address = (u64)tables;
    se3->struct_table_length = len;

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: smbios: Bump to 3.1
......................................................................

Patch Set 1: Code-Review+1

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Patrick Rudolph (Code Review)]

Hello build bot (Jenkins), Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44013

to look at the new patch set (#2).

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

arch/x86/smbios: Bump to 3.1

Set the entry point revision to the SMBIOS defined value and bump
version to 3.1. All new fields introduced in 3.1 are already present
and filled with valid data.

Change the type 17 memory speed to MT/s and add a comments to indicate
which unit the fields have.

NEEDS TEST ON ALL PLATFORMS!
SOME BLOBS ADVERTISE MEMORY SPEED IN FALSE UNITS!

Tested on Intel CFL:
The FSP reports memory speed in MT/s even when the comment state different.

Change-Id: Ieaf876d0297fd12b1ddfe8b3a69704ef03225930
Signed-off-by: Patrick Rudolph 
---
M src/arch/x86/smbios.c
M src/include/memory_info.h
M src/include/smbios.h
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/pcengines/apu1/mainboard.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/soc/intel/cannonlake/romstage/romstage.c
7 files changed, 18 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44013/2

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Marcello Sylvester Bauer (Code Review)]

Marcello Sylvester Bauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

Patch Set 2: Code-Review+1

diff `dmidecode -t 17` HEAD~ HEAD on a ThinkPad X220:
```
3c3
< SMBIOS 3.0 present.
---
> SMBIOS 3.1 present.

18c18
<       Speed: 533 MT/s
---
>   Speed: 1066 MT/s

24c24
<       Configured Memory Speed: 533 MT/s
---
>   Configured Memory Speed: 1066 MT/s

42c42
<       Speed: 533 MT/s
---
>   Speed: 1066 MT/s

48c48
<       Configured Memory Speed: 533 MT/s
---
>   Configured Memory Speed: 1066 MT/s

```

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

Patch Set 2:
> Patch Set 2: Code-Review+1
>
> diff `dmidecode -t 17` HEAD~ HEAD on a ThinkPad X220:
> 3c3
> < SMBIOS 3.0 present.
> ---
> > SMBIOS 3.1 present.
> 18c18
> <       Speed: 533 MT/s
> ---
> >       Speed: 1066 MT/s
> 24c24
> <       Configured Memory Speed: 533 MT/s
> ---
> >       Configured Memory Speed: 1066 MT/s
> 42c42
> <       Speed: 533 MT/s
> ---
> >       Speed: 1066 MT/s
> 48c48
> <       Configured Memory Speed: 533 MT/s
> ---
> >       Configured Memory Speed: 1066 MT/s

Sounds reasonable

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44013/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44013/2//COMMIT_MSG@20 
PS2, Line 20: state different.
states otherwise

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Rob Barnes (Code Review)]

Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44013/2/src/include/memory_info.h 
File src/include/memory_info.h:

https://review.coreboot.org/c/coreboot/+/44013/2/src/include/memory_info.h@3... 
PS2, Line 33: 	uint16_t ddr_frequency;
Could we rename this field so there's no confusion. e.g. https://review.coreboot.org/c/coreboot/+/44549

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Patrick Rudolph (Code Review)]

Hello build bot (Jenkins), Michał Żygowski, Angel Pons,  Marcello Sylvester Bauer, Patrick Rudolph, Piotr Król,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44013

to look at the new patch set (#3).

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

arch/x86/smbios: Bump to 3.1

Set the entry point revision to the SMBIOS defined value and bump
version to 3.1. All new fields introduced in 3.1 are already present
and filled with valid data.

Change the type 17 memory speed to MT/s and add a comments to indicate
which unit the fields have.

NEEDS TEST ON ALL PLATFORMS!
SOME BLOBS ADVERTISE MEMORY SPEED IN FALSE UNITS!

Tested on Intel CFL:
The FSP reports memory speed in MT/s even when the comment states
otherwise.

Change-Id: Ieaf876d0297fd12b1ddfe8b3a69704ef03225930
Signed-off-by: Patrick Rudolph 
---
M src/arch/x86/smbios.c
M src/device/dram/ddr3.c
M src/device/dram/ddr4.c
M src/drivers/intel/fsp1_1/romstage.c
M src/include/memory_info.h
M src/include/smbios.h
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/google/cyan/spd/spd.c
M src/mainboard/pcengines/apu1/mainboard.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/northbridge/intel/haswell/raminit.c
M src/soc/amd/common/block/pi/amd_late_init.c
M src/soc/amd/picasso/dmi.c
M src/soc/intel/apollolake/meminit_util_apl.c
M src/soc/intel/apollolake/meminit_util_glk.c
M src/soc/intel/broadwell/romstage/raminit.c
M src/soc/intel/common/smbios.c
M src/soc/intel/denverton_ns/hob_mem.c
M src/soc/intel/icelake/romstage/romstage.c
M src/soc/intel/jasperlake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/tigerlake/romstage/romstage.c
22 files changed, 44 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44013/3

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/44013/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44013/2//COMMIT_MSG@20 
PS2, Line 20: state different.
> states otherwise

Done

https://review.coreboot.org/c/coreboot/+/44013/2/src/include/memory_info.h 
File src/include/memory_info.h:

https://review.coreboot.org/c/coreboot/+/44013/2/src/include/memory_info.h@3... 
PS2, Line 33: 	uint16_t ddr_frequency;
> Could we rename this field so there's no confusion. e.g. https://review.coreboot. […]

Done

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Masanori Ogino (Code Review)]

Masanori Ogino has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

Patch Set 3: Code-Review+1

(1 comment)

Looks good to me in principle, but I have a small question.

https://review.coreboot.org/c/coreboot/+/44013/3/src/soc/intel/common/smbios... 
File src/soc/intel/common/smbios.c:

https://review.coreboot.org/c/coreboot/+/44013/3/src/soc/intel/common/smbios... 
PS3, Line 42: 	dimm->ddr_frequency_mts = frequency;
Why is the frequency not multiplied by 2 here?

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44013/3/src/soc/intel/common/smbios... 
File src/soc/intel/common/smbios.c:

https://review.coreboot.org/c/coreboot/+/44013/3/src/soc/intel/common/smbios... 
PS3, Line 42: 	dimm->ddr_frequency_mts = frequency;
> Why is the frequency not multiplied by 2 here?

It's multiplied on each SoC already

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

Patch Set 3: Code-Review+1

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Masanori Ogino (Code Review)]

Masanori Ogino has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44013/3/src/soc/intel/common/smbios... 
File src/soc/intel/common/smbios.c:

https://review.coreboot.org/c/coreboot/+/44013/3/src/soc/intel/common/smbios... 
PS3, Line 42: 	dimm->ddr_frequency_mts = frequency;
> It's multiplied on each SoC already

I see. Thank you for the explanation.

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Christian Walter (Code Review)]

Christian Walter has uploaded a new patch set (#4) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/44013 )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

arch/x86/smbios: Bump to 3.1

Set the entry point revision to the SMBIOS defined value and bump
version to 3.1. All new fields introduced in 3.1 are already present
and filled with valid data.

Change the type 17 memory speed to MT/s and add a comments to indicate
which unit the fields have.

NEEDS TEST ON ALL PLATFORMS!
SOME BLOBS ADVERTISE MEMORY SPEED IN FALSE UNITS!

Tested on Intel CFL:
The FSP reports memory speed in MT/s even when the comment state different.

Change-Id: Ieaf876d0297fd12b1ddfe8b3a69704ef03225930
Signed-off-by: Patrick Rudolph 
---
M src/arch/x86/smbios.c
M src/include/smbios.h
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/pcengines/apu1/mainboard.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/soc/intel/cannonlake/romstage/romstage.c
6 files changed, 12 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44013/4

[S] Change in coreboot[master]: arch/x86/smbios: Bump to 3.1

[Stefan Reinauer (Code Review)]

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44013?usp=email )

Change subject: arch/x86/smbios: Bump to 3.1
......................................................................

Abandoned