EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 28:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 41: return m_cfg->PcieRpEnableMask
not sure if that is a good idea because the function only returns valid results after the fsp mask w […]
This already done by lookup devicetree. It had run m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()) before call this.
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 57: pcie_is_flag_enabled(cfg[i], PCIE_RP_CLK_REQ_UNUSED)) : m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; : m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = : convert_clk_src_to_fsp(type, cfg[i], i);
this won't be executed when the port is enabled (line 53)
oh... I forgot the ! in line53.. thanks.
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 157: CONFIG_MAX_ROOT_PORTS
why pass that als parameter instead of using it in the function?
What do you mean? I think Kconfig if fine.