[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Revise PCIE port config

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )

Change subject: soc/intel/alderlake: Revise PCIE port config
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Patch Set 34:

(2 comments)

https://review.coreboot.org/c/coreboot/+/48340/34/src/soc/intel/alderlake/ch... 
File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/48340/34/src/soc/intel/alderlake/ch... 
PS34, Line 343: tic inline int pcie_is_flag_enabled(const struct pcie_rp_config pcie_rp,
              : 				enum pcie_rp_flags flag_mask)
              : {
              : 	return pcie_rp.flags & flag_mask ? 1 : 0;
              : }
              : 
not soc-specific

https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... 
File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... 
PS28, Line 157: CONFIG_MAX_ROOT_PORTS
> We plan to add new Kconfig for CPU_RP ports. It would be different size though. […]

ack