EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 15:
(5 comments)
https://review.coreboot.org/c/coreboot/+/48340/15/src/mainboard/google/brya/... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/15/src/mainboard/google/brya/... PS15, Line 5:
unrelated change
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 148: /* This can be used to set 0x70 for clksrcusage */ : PCIE_RP_LAN_PORT = (1 << 5),
I just looked through the UPD description again. This is actually not correct. […]
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 158: uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
@Furquan, Does PEG port have CLKREQ or just need the src? If it just need src, I think I can separat […]
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 28: if ((config->pcie_rp[i].flags & PCIE_RP_ENABLED) == 0)
Same helper as mentioned in the other file can be used here: […]
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 33: m_cfg->PcieClkSrcClkReq[config->pcie_rp[i].clk_req] = : config->pcie_rp[i].clk_src;
No, it is the other way around: […]
Done