5 comments:
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
unrelated change
Done
File src/soc/intel/alderlake/chip.h:
/* This can be used to set 0x70 for clksrcusage */
PCIE_RP_LAN_PORT = (1 << 5),
I just looked through the UPD description again. This is actually not correct. […]
Done
Patch Set #14, Line 158: uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
@Furquan, Does PEG port have CLKREQ or just need the src? If it just need src, I think I can separat […]
Done
File src/soc/intel/alderlake/romstage/fsp_params.c:
Patch Set #14, Line 28: if ((config->pcie_rp[i].flags & PCIE_RP_ENABLED) == 0)
Same helper as mentioned in the other file can be used here: […]
Done
m_cfg->PcieClkSrcClkReq[config->pcie_rp[i].clk_req] =
config->pcie_rp[i].clk_src;
No, it is the other way around: […]
Done
To view, visit change 48340. To unsubscribe, or for help writing mail filters, visit settings.