Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31948 )
Change subject: mb/asrock/h110m: Add PEG Gen3 support ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... File src/mainboard/asrock/h110m/devicetree.cb:
https://review.coreboot.org/#/c/31948/5/src/mainboard/asrock/h110m/devicetre... PS5, Line 210: # Use SRCCLKREQ0# and CLKSRC0 for PEG x16 root port : register "PcieRpClkReqSupport[0]" = "1" : register "PcieRpClkReqNumber[0]" = "0" : # Enable Latency Tolerance Reporting Mechanism : register "PcieRpLtrEnable[0]" = "1" : register "PcieRpClkSrcNumber[0]" = "0" :
These settings are for the root ports at the PCH, AIUI.
Yes you are right. Usually these parameters are used to configure PCH. But if we look at the description of these options:
https://github.com/IntelFsp/FSP/blob/master/KabylakeFspBinPkg/Include/FspsUp... https://github.com/IntelFsp/FSP/blob/master/KabylakeFspBinPkg/Include/FspsUp...
It says nothing about PCH. In addition, there are no similar parameters for PEG ports. I think FSP uses these options to initialize the PEG. In the case of this board, the PEG port uses the signals CLKOUT0 and CLKREQ0 from PCH. If I do not do these steps, then the PEG port training will be successful only by Gen1.