[coreboot-gerrit] Change in coreboot[master]: vendorcode/intel: Remove Ice Lake, Commet Lake and Denverton FSP Bind...

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37579 )

Change subject: vendorcode/intel: Remove Ice Lake, Commet Lake and Denverton FSP Bindings
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Patch Set 6:

(1 comment)

We should give people a chance to test coreboot+GitHub FSP
before moving forward. IIRC, Ice Lake worked on a WIP port
during 36C3, what about Comet Lake? Denverton?

https://review.coreboot.org/c/coreboot/+/37579/6/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/37579/6/src/soc/intel/tigerlake/rom... 
PS6, Line 43: 
There is no way to predict if the official headers will lack it. And
I doubt if this is build tested.