Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36457 )
Change subject: soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi ......................................................................
soc/intel/{cnl,icl}: Move globalnvs.asl into common/block/acpi
This patch creates a common instance of globalnvs.asl inside intel common code (soc/intel/common/block/acpi/acpi) and ask cnl & icl soc code to refer globalnvs.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS.
Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/dragonegg/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/intel/cannonlake_rvp/dsdt.asl M src/mainboard/intel/coffeelake_rvp/dsdt.asl M src/mainboard/intel/icelake_rvp/dsdt.asl D src/soc/intel/cannonlake/acpi/globalnvs.asl R src/soc/intel/common/block/acpi/acpi/globalnvs.asl 9 files changed, 8 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/36457/1
diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl index ab0b977..8a43784 100644 --- a/src/mainboard/google/dragonegg/dsdt.asl +++ b/src/mainboard/google/dragonegg/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/icelake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/icelake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl index 2568800..5ffdf18 100644 --- a/src/mainboard/google/drallion/dsdt.asl +++ b/src/mainboard/google/drallion/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl index e2959a7..344e4a7 100644 --- a/src/mainboard/google/hatch/dsdt.asl +++ b/src/mainboard/google/hatch/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index 58e0704..22e283f 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
/* global NVS and variables */ - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */ #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl index c719d23..5f4a349 100644 --- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl index 70d0bd6..c5f1136 100644 --- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl +++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl @@ -29,7 +29,7 @@ #include <soc/intel/cannonlake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/cannonlake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
Scope (_SB) { Device (PCI0) diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl index ad469fa..15890f1 100644 --- a/src/mainboard/intel/icelake_rvp/dsdt.asl +++ b/src/mainboard/intel/icelake_rvp/dsdt.asl @@ -30,7 +30,7 @@ #include <soc/intel/icelake/acpi/platform.asl>
// global NVS and variables - #include <soc/intel/icelake/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
// CPU #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/soc/intel/cannonlake/acpi/globalnvs.asl b/src/soc/intel/cannonlake/acpi/globalnvs.asl deleted file mode 100644 index 940cf43..0000000 --- a/src/soc/intel/cannonlake/acpi/globalnvs.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Global Variables */ - -Name (\PICM, 0) // IOAPIC/8259 - -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External (NVSA) - -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PCNT, 8, // 0x03 - Processor Count - PPCM, 8, // 0x04 - Max PPC State - TLVL, 8, // 0x05 - Throttle Level Limit - LIDS, 8, // 0x06 - LID State - PWRS, 8, // 0x07 - AC Power State - CBMC, 32, // 0x08 - 0x0b AC Power State - PM1I, 64, // 0x0c - 0x13 PM1 wake status bit - GPEI, 64, // 0x14 - 0x17 GPE wake status bit - DPTE, 8, // 0x1c - Enable DPTF - NHLA, 64, // 0x1d - 0x24 NHLT Address - NHLL, 32, // 0x25 - 0x28 NHLT Length - CID1, 16, // 0x29 - 0x2a Wifi Country Identifier - U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap - U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap - UIOR, 8, // 0x2f - UART debug controller init on S3 resume - - /* ChromeOS specific */ - Offset (0x100), - #include <vendorcode/google/chromeos/acpi/gnvs.asl> -} diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl similarity index 96% rename from src/soc/intel/icelake/acpi/globalnvs.asl rename to src/soc/intel/common/block/acpi/acpi/globalnvs.asl index 678ce5a..8e8241b 100644 --- a/src/soc/intel/icelake/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -30,7 +30,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - Offset (0x00), OSYS, 16, // 0x00 - Operating System SMIF, 8, // 0x02 - SMI function PCNT, 8, // 0x03 - Processor Count