Attention is currently required from: Tristan Corrick, Arthur Heymans, Iru Cai (vimacs). Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30890 )
Change subject: autoport: Add support for Haswell-LynxPoint platform ......................................................................
Patch Set 22:
(9 comments)
File util/autoport/azalia.go:
https://review.coreboot.org/c/coreboot/+/30890/comment/11749886_76f8137c PS1, Line 66: RegisterPCI(0x8086, 0x0c0c, azalia{})
Mini-HD audio config is hardcoded in `nb/intel/haswell/minihd.c`. Is […]
Gone
File util/autoport/haswell.go:
https://review.coreboot.org/c/coreboot/+/30890/comment/4b3c3e82_2a7f7860 PS22, Line 12: */ This should have a space
https://review.coreboot.org/c/coreboot/+/30890/comment/c87aafba_bc4621ee PS22, Line 50: dq_pins_interleaved Only matters for ULT. You can derive this from the DDR_SCRAM_MISC_CONTROL register:
const bool dq_pins_interleaved = !(MCHBAR32(0x2008) & 1 << 10)
https://review.coreboot.org/c/coreboot/+/30890/comment/0230c378_866bf45e PS22, Line 74: /* FIXME:XX hardcoded. */ : "c1_acpower": cstate[0], : "c2_acpower": cstate[1], : "c3_acpower": cstate[2], : "c1_battery": cstate[0], : "c2_battery": cstate[1], : "c3_battery": cstate[2], We no longer have C-states in the devicetree for Haswell.
File util/autoport/lynxpoint.go:
https://review.coreboot.org/c/coreboot/+/30890/comment/8773f8b8_502c45bc PS1, Line 228: PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, : PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"},
We're not handling this for sandybridge
Done
https://review.coreboot.org/c/coreboot/+/30890/comment/99f8482d_d7819f72 PS1, Line 356: 0x0040
These values depend on the trace lengths for USB and are documented somewhere, I think
Done
File util/autoport/lynxpoint.go:
https://review.coreboot.org/c/coreboot/+/30890/comment/88dc7d70_de73ec5b PS13, Line 326: 1
Not a problem anymore, it's determined automatically at runtime based on PCI IDs. […]
Done
https://review.coreboot.org/c/coreboot/+/30890/comment/0baea527_31e2d7e0 PS13, Line 585: /* SDIO */ : RegisterPCI(0x8086, 0x9c35, GenericPCI{}) : : /* Smart Sound Technology Controller */ : RegisterPCI(0x8086, 0x9c36, GenericPCI{}) : : /* Serial I/O */ : for id := uint16(0x9c60); id <= 0x9c66; id++ { : RegisterPCI(0x8086, id, GenericPCI{}) : }
These probably don't apply to desktops
These don't exist on non-LP.
File util/autoport/lynxpoint.go:
https://review.coreboot.org/c/coreboot/+/30890/comment/25d2bf66_f6021c1f PS22, Line 593: gnvs := Create(ctx, "acpi_tables.c") I would not generate this file at all.