[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Add ADL-P ramstage mainboard code

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46265 )

Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... 
File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/46265/5/src/mainboard/intel/adlrvp/... 
PS5, Line 91: s0ix_enable
> Alright. I wanted to know because S0ix entry requirements are somewhat unclear.

Yes, you are right, its not just depends in this config there are other SOC related FW also and HW IP might also block S0ix but this is basic to have required ACPI and C-states getting exposed.